Hiding Memory Elements in Induced Hierarchical Verification of Speed- Independent Circuits

The goal of induced hierarchical verification techniques is to automatically create hierarchy in an originally flat circuit in order to decompose the verification problem (i.e., checking hazard-freedom and conformance to a specification) into that of verifying a set of smaller sub-circuits. Existing induced hierarchical verification techniques for speed-independent circuits are limited because the output of any memory element (e.g., Muller C-element) must be a sub-circuit output (i.e., memory elements cannot be hidden). Consequently, these techniques have exponential complexity in the number of memory element outputs in the circuit. In this paper, we prove that this limitation is not fundamental. Specifically, we develop a theoretical framework for induced hierarchical verification of speed-independent circuits and show that, under certain well-defined conditions, sub-circuits can be formed which may contain memory elements whose outputs are internal to the sub-circuit. The key step of the approach is to obtain a safe abstraction of the behavior of a set of observationally-sufficient external signals. We prove that such a safe abstraction can drive the reduction of the verification problem into one of verifying a set of smaller sub-circuits. We show how a class of safe abstractions can be derived using an efficient partial order technique. Although generally applicable, we show the result is particularly easy to apply and useful when verifying whether sequential decompositions in speed-independent circuits preserve hazard-freedom.